1. Field of the Invention
The present invention relates to a MIS semiconductor device and a method of manufacturing thereof and, more particularly, to an improvement of a method for manufacturing source and drain regions of a MIS transistor comprising a silicide structure reducing wiring resistance and the like and a LDD (Lightly Doped Drain) structure preventing a short channel effect.
2. Description of the Background Art
A semiconductor device having a stacked structure of metal-insulator-semiconductor is called a MIS semiconductor device. A transistor using an oxide film as the insulator is especially called a MOSFET (Field Effect Transistor). FIG. 4 shows a cross sectional structure of a typical MOSFET. The MOSFET comprises a pair of source.multidot.drain regions (n type) 12.multidot.12 on a surface of a silicon substrate 1, a gate oxide film 2 formed on the substrate between the source.multidot.drain regions, and a gate electrode 3 formed on the surface of the gate oxide film 2. The surface area of the substrate between the source.multidot.drain regions 12.multidot.12 is called a channel region 8. The length of the channel region 8 is represented by the reference character L in the figure.
In operation, a prescribed potential V.sub.D is applied between the source.multidot.drain 12.multidot.12. When a gate voltage V.sub.G larger than the threshold voltage V.sub.TH is applied to the gate electrode 3, an n type inverted layer 20 where electrons are induced is formed in the channel region 8. Consequently, a drain current ID flows between the source and the drain 12.multidot.12. A depletion layer 30 extends around the source and the drain regions 12.multidot.12.
A structure of a MIS (Metal Insulator Semiconductor) transistor has been miniaturized as technique for high degree of integration density and high speed responsiveness in a semiconductor device has made advances. The MIS transistor is miniaturized by shortening a channel length or forming source and drain regions having a shallow junction in accordance with a scaling rule in principle.
However, the following two problems have arisen along with the miniaturization of the MIS transistor.
(1) The short channel effect due to the shortening of the channel of the transistor becomes conspicuous.
Because of the short channel effect, a breakdown phenomenon and a hot electron effect are generated in the vicinity of the drain, so that a life for reliability is decreased and the transistor characteristic is degraded.
One of the short channel effects is hot electron effect. Referring to FIG. 5, a strong electric field is generated near the drain of a MISFET (MOSFET) having a short channel. Electrons introduced to this strong electric field region generate hot carriers by impact ionization. Part of the generated hot carriers are caught by traps or the like in the gate oxide film 2 of the MOSFET and are accumulated as time passes. The accumulated carriers cause changes of the threshold voltage V.sub.TH with time and deterioration of mutual conductance, significantly reducing the reliability of the MOSFET.
(2) Wiring resistance of an impurity diffusion layer and a gate electrode layer becomes conspicuous.
At the source.multidot.drain regions, the resistance is increased as the junction depth becomes shallower and a conductive area becomes smaller. At the gate electrode, the resistance is increased as the gate length becomes shorter and the conductive area becomes smaller.
Because of the increase in wiring resistance, the high speed responsiveness of the transistor is degraded.
As a structure for eliminating these problems, an LDD structure was adopted to prevent the short channel effect and, in addition, as a structure for preventing the increase in wiring resistance, a silicide, structure was proposed. FIG. 6 is a diagram of a conventional MIS transistor having such structure.
Referring to the figure, a gate electrode 3 comprising polysilicon is formed on a p type silicon substrate 1 through a gate oxide film 2. Sidewall spacers and 4 serving as insulating films are formed on either side of the gate electrode 3. n.sup.- impurity regions 5 and 5 with low concentration are formed at a self-aligning position with the gate electrode 3 on the p type silicon substrate 1. In addition, n.sup.+ impurity regions 6 and 6 with high concentration are formed at a self-aligning position with the sidewall spacers 4 and 4. Each n.sup.- impurity region 5 and n.sup.+ impurity region 6 constitute a source and drain region 12 of the transistor. In addition, a structure of the impurity region having a structure in which the positions of the n.sup.- impurity region 5 with low concentration and the n.sup.+ impurity region 6 with high concentration are offset is referred to as a LDD structure. Also, silicide layers 7a, 7b and 7b comprising titanium silicide are formed on the upper surface of the gate electrode 3 and the surface of the n.sup.+ impurity regions 6 and 6. A structure of the silicide layers 7a, 7b and 7b formed in a self-alignment manner on the gate electrode 3 and the n.sup.+ impurity regions 6 and 6 is referred to as a "salicide structure".
The n.sup.- impurity regions 5 and 5 with low concentration constituting the LDD structure are structured such that impurity concentration distribution between the n.sup.+ impurity regions 6 and 6 with high concentration and a channel region 8 just beneath the gate electrode 3 may be made gently-sloping. As a result, electric field concentration particularly on the side of the drain region is mitigated and the generation of the breakdown phenomenon and hot carriers are restrained.
In addition, the silicide layers 7a and 7b constituting the salicide structure is superior in conductivity. The wiring resistance of the gate electrode 3 and the sheet resistance of the source and drain regions 12.multidot.12 are reduced in virtue of this excellent conductivity.
However, the LDD MOSFET additionally causes the following two problems.
The first problem is that the newly disposed n.sup.- impurity region at low concentration constitutes a parasitic resistance to thereby reduce the driving performance of the MOSFET. This is to be explained referring to FIGS. 7A and 7B.
The operation of MOSFET is divided in two types, that is, a pentode region in which the drain voltage V.sub.D is greater than the gate voltage V.sub.G (FIG. 7A) and a triode region in which the gate voltage V.sub.G is much greater than the drain voltage V.sub.D (FIG. 7B). In the pentode region shown in FIG. 7A, a depleted high resistance region is formed between the inversion layer 8 and the drain regions 5a, 6a comprising n.sup.- /n.sup.+ impurity region. In addition to the resistance of a channel comprising the inversion layer 8, the resistance R1 of the n.sup.- impurity region 5b at low concentration on the side of the source, as the parasitic resistance, result in the reduction of the drain current. Further, in the triode region, the resistance R1 of the n.sup.- impurity region 5b on the side of the source and the resistance R2 of the n.sup.- impurity region 5a on the side of the drain, as the parasitic resistance, lower the driving performance of the MOSFET.
The second problem is relevant to hot carriers. That is, in the drain structure of conventional LDD MOSFETs, hot carriers having greater energy than the thermal equilibrium state are formed on the surface of the n.sup.- impurity region 5a at low concentration and the thus generated hot carriers are implanted into the sidewall spacers 4 of the gate electrode 3. As a result, the surface of the n.sup.- impurity region 5a on the side of the drain is depleted, by which the resistance in this region is increased to deteriorate the drain characteristics of the MOSFET.
Referring to FIGS. 8A to 8D, a description is made of manufacturing steps of the conventional MIS transistor shown in FIG. 6.
Referring to FIG. 8A, a thin gate oxide film 2 is formed on a p type silicon substrate 1. Then, a polysilicon layer is formed on the surface of the gate oxide film 2 to form a gate electrode 3 by patterning the gate oxide film 2 and the polysilicon layer. n type impurity ions 9 are implanted on the p type silicon substrate 1 with a small dosage using the gate electrode 3 as a mask to form n.sup.- impurity regions 5 and 5.
Referring to FIG. 8B, a silicon oxide film of the thickness of 2000-3000.ANG. is formed on the p type silicon substrate 1 on which the gate electrode 3 was formed. Then, sidewall spacers 4 and 4 are formed on either side of the gate electrode 3 by performing anisotropic etching on this silicon oxide film. Next, the n type impurity ions 9 are implanted on the p type silicon substrate 1 with a large dosage using this sidewall spacers 4 and 4 and the gate electrode 3 as a mask to form n.sup.+ impurity regions 6 and 6.
Referring to FIG. 8C, a refractory metal layer 11 such as titanium is evaporated on the surface of the p type silicon substrate 1, the gate electrode 3 and the sidewall spacers 4 and 4. Thereafter, high temperature heat treatment is performed and the refractory metal layer 11 is made to react with the polysilicon layer of the gate electrode 3 in contact with this refractory metal layer 11 to form a silicide layer of the refractory metal layer 11 on the region between both layers. The heat treatment was done by RTA lamp annealing method in N.sub.2 gas atmosphere at 600.degree. C.
Referring to FIG. 8D, silicide layers 7a, 7b and 7b are formed in a self-alignment manner on the surface of the gate electrode 3 and the n.sup.+ impurity regions 6 and 6 by removing the unreacted refractory metal layer 11 evaporated on the surface of the sidewall spacers 4 and 4.
As shown in FIGS. 8A to 8D, the sidewall spacers 4 and 4 fulfill two functions. First, they function as a mask to selectively form the silicide layer of the refractory metal layer 11. The sidewall spacer does not react with the refractory metal layer 11. Therefore, the regions on which the refractory metal layer 11 is silicified are separately formed in a self-alignment manner by the sidewall spacer on the surface of the gate electrode 3 and the source and drain region. In order to perform this separation reliably, the thickness t.sub.s of the sidewall spacer 4 is to be 2000-3000.ANG..
Secondly, it functions to define the offset length l.sub.off of the n.sup.- impurity region 5 and n.sup.+ impurity region 6 of the source and drain region. That is, the length of the n.sup.- impurity region 5 constituting the LDD structure is substantially defined by the film thickness of this sidewall spacer 4. However, since the thickness of the sidewall spacer 4 is formed thickly because of the first function, the length of the n.sup.- impurity region 5 is also formed long. This n.sup.- impurity region 5 controls the short channel effect by mitigating an electric field concentration and preventing the generation of the breakdown phenomenon, while serving as parasitic resistance. The longer the n.sup.- impurity region 5 becomes, the more the parasitic resistance increases, so that a problem degrading the responsiveness of a transistor has become noticeable.